"Chris M. Thomasson" <no@[EMAIL PROTECTED]
> wrote in message
news:7ImEk.572$kc.394@[EMAIL PROTECTED]
> "Dmitriy V'jukov" <dvyukov@[EMAIL PROTECTED]
> wrote in message
> news:dd05d47f-9502-43a0-ac49-844bbe34c6c7@[EMAIL PROTECTED]
> On Sep 29, 5:02 pm, "Chris M. Thomasson" <n...@[EMAIL PROTECTED]
> wrote:
>
>> > You mean:
>> >
>> > 1 atomic RMW and 1 StoreLoad membar for lock
>> > 1 atomic RMW and 1 LoadStore membar for unlock
>> >
>> > 2 atomics, and 2 membars; fairly expensive... Well... You indeed have
a
>> > good
>> > point in the case that stealing is rare...
>
>
>> No, I mean for spin-mutex:
>> 1 atomic RMW + 1 StoreLoad membar for lock
>> store-release for unlock
>
> Ahhh, I fail see spin-mutex and thing adaptive mutex.
Let me rephrase...
I see spin-mutex and thought adaptive mutex.
> Sorry for my confusion.
:^/
>> Which for x86 means:
>> 1 atomic RMW for lock (StoreLoad is implied, and so basically
>> costless)
>
> IMHO, its not costless. Not at all...
Bus locking slow-path... Cache locking fast-path...
>> plain store for unlock (release is implied)
>
> Indeed.
Even this operation has excessive costs when compared to an arch that does
not have these implied membars... RMO SPARC has its advantages indeed. TSO
compared to RMO? Which one is more light weight and able to scale... I
personally prefer a fine-grain model over TSO any day...
|
