On 21 sep, 14:36, "Chris M. Thomasson" <n...@[EMAIL PROTECTED]
> wrote:
> <courp...@[EMAIL PROTECTED]
> wrote in message
>
> news:6c1edd55-708e-432a-93f9-224e7ee6b3fd@[EMAIL PROTECTED]
>
>
>
>
>
> > On 21 sep, 14:27, Jon Harrop <j...@[EMAIL PROTECTED]
> wrote:
> >> courp...@[EMAIL PROTECTED]
wrote:
> >> > On 21 sep, 00:12, Jon Harrop <j...@[EMAIL PROTECTED]
> wrote:
> >> >> Within the confines of your assumptions I agree but, in general,
that
> >> >> is
> >> >> not true
>
> >> > What is exactly wrong? that you get the ordering and caching
problem on
> >> > most SMP architectures?
>
> >> The question is whether or not those are always a problem. They are a
> >> problem if determinism is required but determinism is not always
> >> required,
> >> e.g. when caching the results of pure computations.
>
> > I said you get the ordering problem and caching problem on most SMP
> > architectures (i.e they are inherent problems of SMP architectures), I
> > didn't say that you get those problems on all algorithms. In fact, I
> > can write a simple algorithm where no synchronization at all is needed
> > because the shared object is accessed(read and written) concurrently
> > but never used.
> > Back to the topic, without any specific details about the
> > architecture, the RCU, by default, needs memory barriers to access the
> > pointer.
>
> RCU, from the point of reader threads, does NOT need explicit membars to
> access and/or deference the pointer on virtually all major archs out
there;
> DEC Alpha aside for a moment. Dependant load barrier anyone?
Or on any non-CC architectures. As I said, *without any specific
details about the architecture*, RCU needs, by default, membars for
reads and writes. However, for read accesses, membars should indeed
not be needed on most common architectures.
Alexandre Courpron.
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