Re: Enabling multiple timed loops in successive frames of a flat

First, I would recommend reading up on the LV style guide.  You have a
lot of right to left wiring that really creates some spaghetti code. 
In your subVI's, the inputs should flow into the left side and the output
out the right side.  Like wise for case structures.
 
2 things could be causing your problems.  One is using the Stop
function.  That is the equivalent to using the abort button at the
top of LabVIEW.  It brings all code to a screeching halt.  It
should never be used on a block diagram.  Using the abort timed loop
function is similar.  Your are using that has a way to end your timed
loop rather than building your stop condition boolean logic properly. 
(Note, good style puts the continue or stop terminal for a loop to the
lower right.  It was hard to find that terminal since it was buried
in the middle of your loop.)  Are you sure your second times loop is
not executing at least once?  You have some very awkward boolean
logic structures combining together to your case structure that stops the
timed loop.  Not Exclusive Or?  In one leg of that, you are
"Not"ting an XOR of one boolean with a True constant.  If I'm not
mistaken, that is like doing nothing to the original boolean value. 
Perhaps the conditions that caused the first loop to stop are the same in
the second loop and not allowing the 2nd loop to finish.
 
If you use your error wires carefully, it can control the execution of the
code and you won't need so many (if any) frames of the flat sequence
structure.)