COPIED COMP.LANG.FORTH
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VLIW SMP MPP FORTH ROCK ROLL ARCHITECTURE ( SUB-MODEL, RECURSIVE)
( BASED ON MR. MOORE'S ORIGINAL 25X FORTH ENGINE,
AS A TYPE OF SYMMETRIC GRIDDED ( SUPER SCALABLE)
STACK MACHINE MODEL )
---
ZYC STACK MACHINE FOR GENERAL PURPOSE APPLICATION,
AS EXTENSIONS TO MR MOORES 25X PROPOSAL FOR GENERAL PURPOSE APPLICATION
---
RETURN STACK 16 ELEMENTS ( ONE 16-BIT MINIMUM)
PARAMETER STACK 8 ELEMENTS ( ONE 16-BIT MINIMUM, 32 BIT OPS USES X
STACK)
X STACK 4 ELEMENTS ( ONE 16-BIT MINIMUM)
Y STACK 4 ELEMENTS ( ONE 16-BIT MINIMUM)
STATUS STACK 32 ELEMENTS
( TWO 16-BIT MINIMUM, ( PREVIOUS) VALUE AND STATUS PAIR FOR BRANCH
TEST(S))
( RECORDS EVERY STATE CHANGE TO PREVIOUS 32 STEPS FOR ALL STACKS )
ZYC CHIP, ( A FANNED-IN BUT EXTENDED 25X BUS MODEL FOR A
VLIW SMP MPP FORTH DUAL BUS ARCHITECTURE )
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A A A A A
B Y X X X X WHERE X AND Y ARE FORTH MICRO ENGINES FOR A SPECIFIC
B X Y X X X PURPOSE OF BUS TO BUS MESSAGE ROUTING
B X X Y X X ( FUNCTIONING AS N-TO-N WAY BUFFERED CROSSBAR
CUIRCUIT)
B X X X Y X
B X X X X Y
ZYC ZYC ZYC ZYC ZYC WHERE ZYC IS ENHANCED STACK MACHINE
C BUS FOR PARALLEL MULTIPLEXING
C BUS MAY ADDRESS MORE MEMORY THAN 16-BITS
( FOR SCALABILITY)
HOWEVER, ( FOR FAULT TOLERANCE)
A EQUALS B EQUALS C
---
A VLIW SMP MPP FORTH ARCHITECTURE
( FINALLY)
FOUR (4) ZYC CHIP MAY BE USED TO SIMULATE A 16 BY 16 N-TO-N WAY
CROSSBAR FUNCTION FOR CORRECT VLIW SMP MPP FORTH TEST BALANCING.
( IMPLIED BUILT IN)
(a.d., AS AN ENGINEERING NOTE, A FIFTH ZYC CHIP EXECUTING A
/MULTIPLEXING CONTROLER PROGRAM/ MAYBE MORE EFFICIENT FOR ASSISTING
SIMULATION OF MY VLIW SMP MPP FORTH ENGINE WITH AN IMPLIED 15-TO-15-WAY
VLIW SYMMETRIC PARALLEL MULTIPLEXING)
HOPE THIS HELPS SOMEONE, ITS CRAP TO ME!
MAW
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