Re: Big Endian, Little Endian.

clemd@[EMAIL PROTECTED]
 wrote:
> On May 10, 1:08 pm, Sohail Somani <soh...@[EMAIL PROTECTED]
> wrote:
>> cl...@[EMAIL PROTECTED]
 wrote:
>>> On May 9, 8:25 pm, Le Chaud Lapin <jaibudu...@[EMAIL PROTECTED]
> wrote:
>>>> Hi All,
>>>> What header or compile-time trick allows one to determine the byte-
>>>> order of target CPU?
>>> Not possible. Depending on the CPU and the memory system, the byte
>>> order may be dynamic, or it may vary among sections of memory. Or it
>>> may be "mixed endian" (not strictly big or little), or have no
>>> endianness.
>> Wow. Do you have an example?
> 
> Dynamic: HP PA/RISC can switch endianness dynamically.

The MIPS chip that was in the SGI's and DEC pre-Alphas among others
could be switched.   We referred to the DEC version as the SPIM.

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