Re: Big Endian, Little Endian.

On May 10, 1:08 pm, Sohail Somani <soh...@[EMAIL PROTECTED]
> wrote:
> cl...@[EMAIL PROTECTED]
 wrote:
> > On May 9, 8:25 pm, Le Chaud Lapin <jaibudu...@[EMAIL PROTECTED]
> wrote:
> >> Hi All,
>
> >> What header or compile-time trick allows one to determine the byte-
> >> order of target CPU?
>
> > Not possible. Depending on the CPU and the memory system, the byte
> > order may be dynamic, or it may vary among sections of memory. Or it
> > may be "mixed endian" (not strictly big or little), or have no
> > endianness.
>
> Wow. Do you have an example?

Dynamic: HP PA/RISC can switch endianness dynamically.

Vary among sections of memory: in the Intel i960CA, the endianness of
16 memory sections were individually selectable. I don't remember
whether they were dynamic.

Mixed endian: other posters have already mentioned the beloved PDP-11.
In addition to floating point being mixed endian, I recall that long
(32-bit) was also. But that was by software convention; I don't
remember any hardware sup****t for 32-bit integers.

No endianness: I don't have an example, but if all primitive datatypes
have the same size there will be no endianness. In C99 that would mean
that CHAR_BIT == 64 or more, so that the minimum size long long fits
into a single character.

One item to keep in mind: endianness relies on the ability to treat
part of an data item as an array of smaller data items. Many
instruction sets permit this on memory but not on registers. For those
systems it is the memory system and not the processor which has an
endianness. The i960CA example mentioned above is one such case.

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