Dmitriy Vyukov <dvyukov@[EMAIL PROTECTED]
> writes:
> Will it be possible to issue only compiler ordering barrier (release,
> acquire or full), but not hardware ordering barrier in C++0x?
>
> Accesses to volatile variables are ordered only with respect to
> accesses to other volatile variables. What I want it to order access
> to variable with respect to accesses to all other volatile and non-
> volatile variables (w/o any hardware barriers, only compiler
> ordering).
Within a single thread, all operations *are* ordered. The ordering
relations
are happens-before and sequenced-before. A is sequenced-before before B
when
A physically comes before B in the source code, or the sequencing rules
say so
(e.g. lhs of a comma op is sequenced before rhs).
If A is sequenced-before B, then A also happens-before B. If you then
introduce a synchronization edge between thread T1 and thread T2
(e.g. store(mem_order_release) on T1, load(mem_order_acquire) on T2), then
anything that happens-before the store also happens-before the load.
> Such compiler barriers are useful in effective synchronization
> algorithms like SMR+RCU:
> http://sourceforge.net/project/showfiles.php?group_id=127837
> (fastsmr package)
> because they allows one to eliminate all hardware memory barriers from
> fast-path.
All accesses to shared data MUST be synchronized with atomics: if there
are
two accesses to a non-atomic variable, at least one of which is a write,
and
there is NOT a happens-before relation between them, you have a data race,
and
undefined behaviour.
If you can prove that you have a happens-before relation, you're safe,
otherwise you need to do some synchronization, or perhaps use
mem_order_relaxed.
Anthony
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