Re: Cycles per ASM instruction

"Gerard Schildberger" <Gerard46@[EMAIL PROTECTED]
> writes:
> +---------------------------------------------+----------+
> |            CPU                     family   |  approx. |
> |  vendor    model                 model name |   MIPS   |
> +---------------------------------------------+----------+

> |   IBM      2065                   360/65    |      .70 |
> |   IBMrpq   2067                   360/67    |      .98 |
> |   IBMrpq   2067 mp                360/67    |     1.96 |
> |   IBM      2075                   360/75    |      .89 |
> |   IBM      2085-1                 360/85    |     1.92 |
> |   IBM      2085-2                 360/85    |     2.40 |
> |   IBM      2090                   360/90    |     5.00 |
> |   IBM      2091                   360/91    |     5.00 |
> |   IBM      2092                   360/92    |     5.00 |
> |   IBM      2095                   360/95    |     5.00 |
> |                                             |          |
> +---------------------------------------------+----------+

wierd?

360/67-1 was supposedly identical to 360/65 (when running in non-DAT
mode) ... i.e. 750ns memory cycle, 8 byte i-fetch. part of instruction
timing formulae ... includes amortized part of 8byte i-fetch ... i.e.
2byte instructions includes 1/4th of 750ns double-word instruction
fetch, 4byte instructions includes 1/2 of 750ns double-word
instruction fetch. 

A four byte instruction with one storage operand access would
effectively have 1.5*750ns related to storage access (prorated i-fetch
plus one instruction operand) ...  plus whatever the actual
instruction timing is.

in fact, looking at the functional characteristics do***ent for both
machines (off bitsaver) appears to give identical timing values for
every instruction.

turning on dynamic address translation in 360/67 ... added 150ns to
ever memory access ... effectively making it a 900ns memory access
machine instead of 750ns (and all the instruction timings change
appropriately). that makes 67-1 identical to 65 in performance
.... except when dynamic translation is turned on ... when 67-1
effectively is about 20percent slower.

360/67-2 is little more complicated ... as part of multiprocessor
sup****t ... they put in multi-****ted memory ... which slows down every
memory access ... by about 20percent ...  approx. 900ns instead of
750ns (for base hardware, running with dynamic address translation on
then slows it down another 150ns). 

The functional characteristics gives instruction timings for 67-1 and
67-2 with DAT off. The actual times for 67-1 with DAT turned on
.... would be approx the same as the timings for 67-2 (with DAT turned
off).

However, 67-2 under heavy I/O load could have actual higher thruput
than 67-1 ... the multi-****ting memory cutting down on processor
stalls contending for memory bus with i/o activity; i.e.  heavy i/o
load for 65/67-1 probably means more like effective .5mips (and 67-1
running in virtual memory mode, i.e. DAT turned on, would be slower
still).

do***ents at:
http://www.bitsavers.org/pdf/ibm/360/funcChar/


http://www.bitsavers.org/pdf/ibm/360/funcChar/A22-6884-3_360-65_funcChar.pdf
http://www.bitsavers.org/pdf/ibm/360/funcChar/GA27-2719-2_360-67_funcChar.pdf


more wierd:
|   IBM      2091                   360/91    |     5.00 |
|   IBM      3168-3                 370/168   |     2.74 |
|   IBM      3158-3                 370/158   |     1.00 |
|   IBM      4341-1                 370/4341  |      .88 |

here is benchmarks that i did on 158, 3031, and an early engineering
model 4341-1 (machine cycle time was running about 10-15percent slower
than what ****pped to customers):

                  158               3031              4341
Rain          45.64/47.42    |   37.03/37.77   |   36.21/37.57
Rain4         43.90/44.80    |   36.61/36.89   |   36.13/36.51

also times approx;
                  370/145            370/168            360/91
                 145 secs.           9.1 secs          6.77 secs

.... snip ...

4341 rather than about ten percent slower than 158-3 ... was closer to
25percent faster (and customer production machines would have been
faster still)

misc. past posts with old email from days working with 4341
http://www.garlic.com/~lynn/lhwemail.html#4341

158 and 3031 had effectively the same microcode engine. the biggest
change from 158 to 3031 was that the 158 had integrated channel
microcode shared on same engine executing 370 microcode ...  and for
the 303x machines they took the 158 integrated channel microcode and
packaged it as a separate box called a channel director (i.e. a single
processor 3031 was actually two 158 microcode engines ... one
dedicated to channel function and one dedicated to 370 instructions).