Re: optimization possibilities...

In message <-NedndNK0e2y2pfVnZ2dnUVZ_o3inZ2d@[EMAIL PROTECTED]
>, Chris Thomasson
<spamtrap@[EMAIL PROTECTED]
> wrote:

> x86 is TSO such that stores have implied preceding (#LoadStore |
> #StoreStore), and loads have a implied trailing (#LoadStore |
#LoadLoad).
> The only explicit memory barrier you need is (#StoreLoad | #StoreStore)
to
> prevent load-after-store reordering; here is the do***entation:
> 
> http://www.intel.com/products/processor/manuals/318147.pdf

I was working to some earlier Intel docs. I have done some searching and
found re****ts that explicit memory barriers are required on Pentium Pro
and
Winchip processors, and some 486 and Pentium systems. There is sup****t for
such processors in Linux.