Stargazer wrote:
>>> ; Acknowledge interupt with PIC(s).
>>> ; After calling callbacks, to enable nesting of interrupt handlers
>>> according to priorities
>>> ; TODO: check rotation priorities of 8259 and other options
>>> ;
>>> mov al, CMD_EOI
>>> out PIC_MASTER, al
>>> cmp ebx, 8
>>> jb fin
>>> out PIC_SLAVE, al
>> These 2 OUT's are what takes 2000+ cycles. The reason you see it
elsewhere is
>> most likely a bug in your measurement code.
>
> Why would it take 2000+ cycles? interrupt controller is integrated in
> a chipset which provides pretty fast access.
Because i8259 is still an LPC (new name for ISA) device working at the
slow ISA bus speed.
> Anyway, your assertion is
> not true: if I just comment out the "inc dword [_running_irq]", I get
> total latency of about 300 cycles.
This is really strange and intriguing. I assume you've made sure that
your timing code is correct (i.e. uses synchronizing instructions as
Intel recommends). Can you try incrementing a different address, does it
make a difference? An address off SS segment (e.g. inc dword ss:[-4])?
Replace the increment with a mov?
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