On Mar 17, 10:06 pm, "Marven Lee" <spamt...@[EMAIL PROTECTED]
> wrote:
> Stargazer wrote:
> > I measured CPU clocks elapsed between the first assembly instruction
> > executed at interrupt's entry point in IDT and beginning of the C code
> > of user-defined interrupt handler and the result was a big
> > surprise :-) It took about 2500 cycles despite that I have only a
> > handful of assembly instructions before a call to user-supplied IRQ
> > handler.
>
> Is the Celeron 2.8G related to the Pentium 4? I'm not clued up on
> processors of the last few years.
Yes, it's Celeron from Pentium-4 family. However, I don't include
processor's interrupt entry and IRET into timing. For now I want my
interrupt entry code to introduce minimal additional latency, not deal
with matters that I can't change anyway :-)
As I said, I know where the problem lies, but I don't understand the
reason so I can't yet eliminate it.
D
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