Stargazer wrote:
....
> I measured CPU clocks elapsed between the first assembly instruction
> executed at interrupt's entry point in IDT and beginning of the C code
> of user-defined interrupt handler and the result was a big
> surprise :-) It took about 2500 cycles despite that I have only a
> handful of assembly instructions before a call to user-supplied IRQ
> handler.
A ****d IRQ (just EOI and IRET) takes about 200 cycles, if measured in
an unproteced environment (ie: my OS where all code run with PL0).
One big cycle loss is in the PL-transition, especially if hardware
task-switches are in use.
> A little more testing showed that almost all cycles (2300+) were spent
> at access to a global variable (via ds:[] addressing). Nothing that
> accesses stack memory (push, pop, call, mov) makes a noticeable
> difference. Does anybody have an idea why this happens? I test on
> Celeron 2.8G in protected mode set up for flat model with paging
> disabled.
If there is no WBINVD instruction (~2000 cycles) in your code
I can just guess what may happen here
user code runs PL=3...
IRQ : ->PL=0
user hooks : PL0->PL3
global access: PL3->PL0->PL3
end of hook : PL3->PL0
IRET : PL0->PL3
__
wolfgang
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