by Stargazer <spamtrap@[EMAIL PROTECTED]
>
Mar 17, 2008 at 05:50 AM
> Cache latency?
That's the first thing that jumps into mind, but... over 2000 cycles?
OTOH, may it be that L2 cache on Celeron (or on-board L3?) is
organized so badly that it read-modify-write to memory *always* causes
a cache miss? Interesting, I ought to test what happens if there is an
off-chip cache and if I can disable it.
D
