Re: Pax, DEP and Jumping into middle of instructions

In article <TttBj.93$qS5.60@[EMAIL PROTECTED]
>, 
redelm@[EMAIL PROTECTED]
 says...

[ ... ]

> While this is entirely true, I wonder how the Pentium4 and
> its' predecoded "trace cache" would handle it.  Probably with
> a long stall as the bytes were reloaded from memory (L2?) and
> re-decoded.  Other CPUs should be able to draw from L1.

You're right about the P4 -- doing this gives terrible performance with 
it.

You're only sort of half-right about the other CPUs. Even though they 
don't store decoded instructions in the L1 cache, they do store 
information about instruction boundaries, and when this becomes 
incorrect, they lose a fair amount of performance as well. 

-- 
    Later,
    Jerry.

The universe is a figment of its own imagination.