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Re: instruction bundling (scheduling?)

by IndianTechie <kamalpr@[EMAIL PROTECTED] > Apr 14, 2008 at 10:18 PM

On Apr 13, 10:49 pm, andreybokha...@[EMAIL PROTECTED]
 wrote:
> On Apr 9, 11:29 pm, kphillips <kevin.phillip...@[EMAIL PROTECTED]
> wrote:
>
> > One other query - I have no specific algorithms that cater for data
> > prefetches. Since a load instruction take a huge amount of cycles
> > (assuming the worst case scenario - memory), is it a good idea to
> > issue advanced load instructions as early as possible? Then the
> > latency for loads will be assumed for quite less .. hopefully it will
> > work for most cases.

yes -unlike its competitor POWER processor, the itanium processor
depends on the compiler to pre-fetch data. Further, there is no on-
chip scheduler and so best results can only be obtained if compiler
writer schedules instructions appropriately.

> ...and registers' live ranges will be quite longer, leading to higher
> register pressure. You have to use a heuristic here.
>
> Regarding scheduling vs register allocation -- I agree with Anton Ertl
> that it is better to do scheduling first. For two reasons:
> 1. Usually, optimal, unhindered (by new dependencies introduced by
> register allocation) scheduling is more important (no hard data here,
> just my practical observations)

The APIC bundle was designed to schedule instructions in parallel in
such a way that processor utilization can be improved. If you know
that 2 or more instructions can safely execute in parallel either
because they use different functional units with the processor or
because there is no read-write conflict, just bundle them together.

> 2. You have quite a few registers on Itanium (especially if you
> allocate on single basic blocks level and thus, have all of the
> registers free again at the start of each new block)
>
we have quite a few registers on Itanium and there is a register
stack, wherein when you enter a procedure -local variables are
allocated on the register stack and then de-allocated when you exit.
So, the liveness of a variable(register allocation) is of concern only
within a procedure's context.

regards
-kamal

p.:s- I work for a company that sells Itanium boxes/compilers.




 7 Posts in Topic:
instruction bundling (scheduling?)
kphillips <kevin.phill  2008-04-04 09:27:22 
Re: instruction bundling (scheduling?)
anton@[EMAIL PROTECTED]   2008-04-06 16:20:41 
Re: instruction bundling (scheduling?)
kphillips <kevin.phill  2008-04-09 12:29:07 
Re: instruction bundling (scheduling?)
andreybokhanko@[EMAIL PRO  2008-04-13 10:49:18 
Re: instruction bundling (scheduling?)
IndianTechie <kamalpr@  2008-04-14 22:18:40 
Re: instruction bundling (scheduling?)
kphillips <kevin.phill  2008-04-15 11:22:49 
Re: instruction bundling (scheduling?)
Sid Touati <SidTouati@  2008-04-22 11:14:20 

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tan12V112 Sat May 17 0:54:33 CDT 2008.