Many thanks for your feedback!
> Given the large number of registers in IA-64, for simplicity just
> schedule first and allocate registers later; spilling and thus
> rescheduling will be rare. Also, most liveness analysis and register
> allocation algorithms work on scheduled code anyway (if they work
> before instruction scheduling, they use the order coming out of
> earlier phases).
Great. If there is the need for spilling, I will try either to
(1) try to find an empty slot in a template to use
(2) otherwise add an extra template for the load
It's rather simple, but I think it will work
> A nice paper on instruction scheduling and register allocation for
> basic blocks is:
> author = "James R. Goodman and Wei-Chung Hsu",
> title = "Code Scheduling and Register Allocation in Large Basic
Blocks",
Thanks! will go through it very soon.
One other query - I have no specific algorithms that cater for data
prefetches. Since a load instruction take a huge amount of cycles
(assuming the worst case scenario - memory), is it a good idea to
issue advanced load instructions as early as possible? Then the
latency for loads will be assumed for quite less .. hopefully it will
work for most cases.
K. Phillips
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