On Wed, 19 Oct 2005 11:15:05 +0200, Sreeram S wrote:
> I dont understand how the clock phase, polarity and delays between Slave
> select and clock edges are related to using interrupts. In my case
since
> both master and slave are processors, all the parameters are
configurable
> and I wanted to know the factors that are considered while deciding
these
> values.
> The tranmission and reception of one full message frame ( byte ) is
handled
> by hardware. Interrupts are only used for copying into tranmsit register
and
> copying from receive register. Polling does not suit my requirements
since
> both the processors are heavily loaded.
> If the delay between slave select and first clock edge is meerly a set
up
> time for the gates, I feel one clock cycle of the slower device is a
good
> figure
> Regarding the clock phase, both master and slave can latch data on both
the
> edges. so ideally speaking all the phase polarity combinations should
work.
As long as they're both the same, it should work regardless, yes.
And you shouldn't have to worry about that anyway, unless you're
bit-banging it at one end or the other - don't you just write a
byte to the SPI transmitter and it takes care of all the timing,
then when that byte shows up at the receiver, you get an interrupt,
right?
Thanks,
Rich
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