Re: begginer question

Robert Redelmeier wrote in part:

> The MUL and DIV instructions are wired to take only one
> variable operand, and use fixed registers for the other
> operand and destination:

> MUL [src]  does EAX*[src] and puts the results in
>      EAX:EDX  (EAX has the high 32 bits, EDX the low).

> DIV [src]   does EAX:EDX / [src] and puts the
>             result in EAX and the remainder in EDX.


Mmh.. my CPU does it the other way around  :)

MUL [src]  ;does EAX*[src] and puts the result in
           ;EDX:EAX ("EDX has the high 32 bits" ..)
DIV [src]  ;does EDX:EAX/[src] and is therefore prone
           ;to overflow if the result is >32 bit.

> All of this is nicely desribed in the Intel and AMD
> instruction-set manuals.

Yes.

__
wolfgang